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MC14099B 8-Bit Addressable Latches
The MC14099B is an 8-bit addressable latch. Data is entered in serial form when the appropriate latch is addressed (via address pins A0, A1, A2) and write disable is in the low state. For the MC14099B the input is a unidirectional write only port. The data is presented in parallel at the output of the eight latches independently of the state of Write Disable, Write/Read or Chip Enable. A Master Reset capability is available on both parts.
Features
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PDIP-16 P SUFFIX CASE 648 16 MC14099BCP AWLYYWWG 1 16 SOIC-16 DW SUFFIX CASE 751G 1 16 14099BG AWLYYWW
* * * * * * *
Serial Data Input Parallel Output Master Reset Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load over the Rated Temperature Range MC14099B pin for pin compatible with CD4099B Pb-Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V SOEIAJ-16 F SUFFIX CASE 966
MC14099B ALYWG 1
mA mW C C C
A WL, L YY, Y WW, W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
August, 2005 - Rev. 6
Publication Order Number: MC14099B/D
MC14099B
PIN ASSIGNMENT
Q7 RESET DATA WRITE DISABLE A0 A1 A2 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q6 Q5 Q4 Q3 Q2 Q1 Q0
WRITE DISABLE DATA A0 A1 A2 RESET 5 6 DECODER 7 VDD = 16 VSS = 8
MC14099B
4 3 8 9 10 11 12 8 13 LATCHES 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
ORDERING INFORMATION
Device MC14099BCP MC14099BCPG MC14099BDW MC14099BDWG MC14099BDWR2 MC14099BDWR2G MC14099BFEL Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 WB SOIC-16 WB (Pb-Free) SOIC-16 WB SOIC-16 WB (Pb-Free) SOEIAJ-16 Shipping 500 Units / Rail 500 Units / Rail 47 Units / Rail 47 Units / Rail 1000 Units / Tape & Reel 1000 Units / Tape & Reel 2000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II IIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII III II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIII II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII I II I I I I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I III II IIII III I II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIII II IIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I III II IIII I II II IIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII IIIII I I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Quiescent Current (Per Package) Input Capacitance MC14599B -- Data (pin 3) (Vin = 0) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) Output Voltage Vin = VDD or 0 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD Characteristic "1" Level "1" Level "0" Level Source Sink Symbol VOH VOL IOH VIH IDD IOL Cin Cin VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 - - - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11
2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004.
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MC14099B
- - -
-
-
-
- - -
- - -
- 55_C
3 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 - - - - - - - - - - - - - - - - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 IT = (1.5 mA/kHz) f + IDD IT = (3.0 mA/kHz) f + IDD IT = (4.5 mA/kHz) f + IDD - - - - - - - - - - - - 0.00001 Typ (Note 2) - 4.2 - 0.88 - 2.25 - 8.8 0.005 0.010 0.015 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 15 0 0 0 - - - - - - - - - - - - - 0.1 22.5 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 - - - - - - - - - - - - 125_C 1.0 0.05 0.05 0.05 Max 150 300 600 1.5 3.0 4.0 - - - - - - - - - - - - - - - mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc pF pF
II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII II IIIIIIIIIIIIIII II I I II I II IIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIII II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIII I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIII III I II I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I I I I III II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIII IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I IIII I IIIIIIIIII IIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I III IIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I II I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII
5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Removal Time Write Disable to Address
Set Up Time Address to Write Disable
Hold Time Write Disable to Data
Set Up Time Data to Write Disable
Write Disable
Pulse Widths Reset
Propagation Delay Time, MC14599B only Chip Enable, Write/Read to Data
Propagation Delay Time Data to Output Q
Output Rise and Fall Time tTLH, tTHL = (1.35 ns/pF) CL + 32 ns tTLH, tTHL = (0.6 ns/pF) CL + 20 ns tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
Address to Data
CE to Output Q (MC14599B only)
Reset to Output Q
Write Disable to Output Q
Characteristic
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Symbol
MC14099B
tPHL, tPLH
tPHL, tPLH
tTLH, tTHL
tw(H) tw(L)
trem
tsu
tsu
th
4 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min 100 80 40 150 75 50 100 50 35 320 160 120 150 75 50 - - - - - - - - - - - - - - - - - - - - - 0 0 0 Typ (Note 6) - 80 - 40 - 40 160 80 60 200 90 75 200 80 65 225 100 75 175 80 65 200 80 60 200 75 50 100 50 40 45 30 10 75 40 25 50 25 20 75 40 25 Max 400 180 150 400 160 130 450 200 150 350 160 130 400 160 120 400 150 100 200 100 80 - - - - - - - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
MC14099B
FUNCTION DIAGRAM
RESET 2 9 Q0 DATA 3 WRITE 4 DISABLE TO OTHER LATCHES A0 5
EACH LATCH
ZERO SELECT
10 Q1 11 Q2 12 Q3
A1 6
ADDRESS DECODER
OTHER LATCHES
13 Q4 14 Q5 15 Q6 1 Q7
A2 7 (M.S.B.)
TRUTH TABLE
Write Disable 0 0 1 Reset 0 1 0 Addressed Latch Data Data Qn* Unaddressed Latches Qn* Reset { Qn* Reset CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on the address inputs A0, A1, and A2.
1 1 Reset *Qn is previous state of latch. Reset to zero state.
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MC14099B
SWITCHING WAVEFORMS
DATA OR WRITE DISABLE
VDD 50% VSS tPLH 90% 50% 10% tTLH tTHL WRITE DISABLE tw(H) VDD tPHL VDD ADDRESS 50% VSS tsu tw(L) 50% VSS tsu DATA 50% VSS th VDD trem VDD
OUTPUT Q
RESET
50% VSS tPHL
OUTPUT Q
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MC14099B
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 WB DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE C
D
16 M 9
A
q
h X 45_
0.25
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
H
M
B
8X
1
8
16X
B TA
S
0.25
M
B
S
A
E B
A1
14X
e
SEATING PLANE
T
C
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L
MC14099B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC14099B/D

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